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description the CXP921F064A is a cmos 16-bit microcomputer integrating on a single chip an a/d converter, serial interface, i 2 c bus interface, timer, clock prescaler, remote control receive circuit, and as well as basic configurations like a 16-bit cpu, rom, ram, and i/o port. this lsi also provides the sleep/stop functions that enable lower power consumption. features an efficient instruction set as a controller direct addressing, numerous abbreviated forms, multiplication and division instructions instruction sets for c language and rtos highly quadratic instruction system, general- purpose register of 16-bit 8-pin 16-bank configuration minimum instruction cycle 100ns at 20mhz operation (2.7 to 3.3v) 61s at 32khz operation (2.2 to 3.3v) incorporated flash rom capacity 256k bytes incorporated ram capacity 10k bytes peripheral functions a/d converter 8-bit 12 analog input, 2 channels, successive approximation system, automatic scanning function, (conversion time: 3.4s at 20mhz) serial interface 128-byte buffer ram, 3 channels 8-stage fifo, 1 channel (supports special mode master/slave) ? 2 c bus interface 64-byte buffer ram , 2 channels (supports master/slave and automatic transfer mode) timers 8-bit timer/counter, 2 channels (with timing output) 16-bit timer, 3 channels real-time pulse generator 5-bit output, 1 channel (2-stage fifo) clock prescaler remote control receive circuit 8-bit pulse measurement counter, 8-stage fifo interruption 30 factors, 30 vectors, multi-interruption and priority selection possible standby mode sleep/stop package 100-pin plastic qfp/lqfp 104-pin plastic lflga mask rom cxp921064a piggy/evaluation chip cxp921000a structure silicon gate cmos ic cmos 16-bit single chip microcomputer ?1 e00250a18-ps sony reserves the right to change products and specifications without prior notice. this information does not convey any licens e by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustr ating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits. CXP921F064A 100 pin qfp (plastic) 100 pin lqfp (plastic) 104 pin lflga (plastic)
?2 CXP921F064A block diagram pa0 to pa7 pb0 to pb7 pc0 to pc7 pd0 to pd7 pe0 to pe7 pf0 to pf3 pf4 to pf7 pg0 to pg7 ph6, ph7 ph0 to ph5 pi0 to pi7 pj0 to pj7 cs0 so0 si0 sck0 si1 cs1 sck1 so1 cs2 so2 si2 sck2 to tmo ec rmc port a buffer ram i 2 c bus interface unit (ch1) buffer ram i 2 c bus interface unit (ch0) fifo serial interface unit (ch3) buffer ram serial interface unit (ch2) buffer ram serial interface unit (ch1) buffer ram serial interface unit (ch0) 8 8 16 port b 8 port c 8 port d 8 port e 8 port f 4 4 2 8 6 port g 8 port h port i port j 8 spc950 cpu core clock generator/ system controller flash rom 256k bytes boot rom ram 10k bytes prescaler/ time-base timer so3 si3 sck3 scl0 sda0 scl1 sda1 int0 to int7 ks0 to ks15 nmi rst tex tx extal xtal v dd v ss 5 a/d converter (ch0) 12 12 remocon fifo 16-bit timer (ch2) 16-bit timer (ch1) 16-bit timer (ch0) interrupt controller an0 to an11 an12 to an23 rto0 to rto4 av ref0 av ss rxd txd teta tetb tetc pwe av ref1 av dd xout 8-bit timer/counter (ch0) 8-bit timer (ch1) 3 2 2 2 realtime pulse generator fifo tokei prescaler a/d converter (ch1) simple uart flash controller
3 CXP921F064A pin assignment 1 (top view) 100-pin qfp package 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 pe7 pf0 pf1/ec pf2/cs0 pf3/si0 pf4/so0 pf5/sck0 pf6/to/tetb pf7/tmo/teta rst v ss xtal extal v dd pg0/cs1 pg1/si1 pg2/so1 pg3/sck1 pg4/cs2 pg5/si2 pj0/an4/ks8 av dd av ref1 av ref0 avss an3 an2 an1 pi7/an0 pi6/nmi pi5/int7 pi4/int6 pi3/int5 pi2/int4 pi1/int3 pi0/int2 ph7/int1/tetc ph6/int0 ph5/xout ph4/rto4 ph3/rto3 ph2/rto2 ph1/rto1 ph0/rto0 vss 51 52 53 54 55 56 tx tex v dd pg7/sck2 pg6/so2 pb2/an22 pb3/an23 pb4/si3 pb5/so3 pb6/sck3 pb7/rmc pc0/sda0 pc1/scl0 pc2/sda1 pc3/scl1 pc4 pc5 pc6 pc7 v ss pd0/ks0 pd1/ks1 pd2/ks2 pd3/ks3 pd4/ks4 pd5/ks5 pd6/ks6 pd7/ks7 pe0/txd 25 26 27 28 29 pe1/rxd pe2 pe3 pe4 pe5 30 pe6 pb1/an21 pb0/an20 pa7/an19 pa6/an18 pa5/an17 pa4/an16 pa3/an15 pa2/an14 pa1/an13 pa0/an12 v ss v dd pwe pj7/an11/ks15 pj6/an10/ks14 pj5/an9/ks13 pj4/an8/ks12 pj3/an7/ks11 pj2/an6/ks10 pj1/an5/ks9 100 note) 1. vss (pins 15, 41, 56 and 90) must be connected to gnd. 2. v dd (pins 44, 53 and 89) must be connected to v dd .
4 CXP921F064A pin assignment 2 (top view) 100-pin lqfp package 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 pe7 pf0 pf1/ec pf2/cs0 pf3/si0 pf4/so0 pf5/sck0 pf6/to/teta pf7/tmo/tetb rst v ss xtal extal v dd pg0/cs1 pg1/si1 pg2/so1 pg3/sck1 pg4/cs2 pg5/si2 pj0/an4/ks8 av dd av ref1 av ref0 avss an3 an2 an1 pi7/an0 pi6/nmi pi5/int7 pi4/int6 pi3/int5 pi2/int4 pi1/int3 pi0/int2 ph7/int1/tetc ph6/int0 ph5/xout ph4/rto4 ph3/rto3 ph2/rto2 ph1/rto1 ph0/rto0 vss 51 52 53 54 55 56 tx tex v dd pb4/si3 pb5/so3 pb6/sck3 pb7/rmc pc0/sda0 pc1/scl0 pc2/sda1 pc3/scl1 pc4 pc5 pc6 pc7 v ss pd0/ks0 pd1/ks1 pd2/ks2 pd3/ks3 pd4/ks4 pd5/ks5 pd6/ks6 pd7/ks7 pe0/txd 25 26 27 28 29 pe1/rxd pe2 pe3 30 pe4 pe5 pe6 pb1/an21 pb2/an22 pb3/an23 pb0/an20 pa7/an19 pa6/an18 pa5/an17 pa4/an16 pa3/an15 pa2/an14 pa1/an13 pa0/an12 v ss v dd pwe pj7/an11/ks15 pj6/an10/ks14 pj5/an9/ks13 pj4/an8/ks12 pj3/an7/ks11 pj2/an6/ks10 pj1/an5/ks9 100 pg7/sck2 pg6/so2 note) 1. vss (pins 13, 39, 54 and 88) must be connected to gnd. 2. v dd (pins 42, 51 and 87) must be connected to v dd .
5 CXP921F064A pin assignment 3 (top view) 104-pin lflga package 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 12345678910111213 pb1 pa7 pa4 pa1 v ss nc pj5 pj2 pj0 a a pb2 pb0 pa5 pa2 v dd pj7 pj4 pj1 av dd b b pb6 pb5 pb3 pa6 pa3 pa0 pj6 pj3 av ref1 av ss an3 c c pc0 pb7 pb4 av ref0 an2 an1 d d pc3 pc2 pc1 pi7 pi6 pi5 e e pc6 pc5 pc4 pi4 pi3 pi2 f f v ss pc7 pd0 pi1 ph7 pi0 g g pd1 pd2 pd3 ph4 ph5 ph6 h h pd4 pd5 pd6 ph1 ph2 ph3 j j pd7 pe0 pe3 v dd v ss ph0 k k pe1 pe2 pe4 pf1 pf4 v ss v dd pg2 pg7 tex tx l l pe5 pe7 pf2 pf5 pf7 extal pg1 pg4 pg6 m m pe6 pf0 pf3 pf6 rst xtal pg0 pg3 pg5 n n 12345678910111213 note) 1. vss (pins 13, 39, 54 and 88) must be connected to gnd. 2. v dd (pins 42, 51 and 87) must be connected to v dd . 3. pin nos. 1 to 100 are the same pin nos. of lqfp. for details, see page 4.
6 CXP921F064A pin functions symbol i/o functions pa0/an12 to pa7/an19 output / input (port a) 8-bit output port. (8 pins) output / input output / input output / output output / i/o output / input i/o / i/o i/o / i/o i/o / i/o i/o / i/o i/o (port b) 8-bit output port. (8 pins) pb0/an20 to pb3/an23 pb4/si3 pb5/so3 pb6/sck3 pb7/rmc pc0/sda0 pc1/scl0 pc2/sda1 pc3/scl1 pc4 to pc7 pf0 pf1/ec pf2/cs0 pf3/si0 pf4/so0 pf5/sck0 pf6/to/tetb pf7/tmo/teta input input / input input / input input / input output / output output / i/o output / output output / output (port c) 8-bit i/o port. i/o can be specified in 1-bit units. pull-up resistor is present or not through program in 1-bit units. (8 pins) (port d) 8-bit i/o port. i/o can be specified in 1-bit units. can drive 5ma sink current (v dd = 2.7 to 3.3v). (8 pins) pd0/ks0 to pd7/ks7 pe0/txd pe1/rxd pe2 to pe7 i/o / input (port e) 8-bit i/o port. i/o can be specified in 1-bit units. (8 pins) (port f) 8-bit port. lower 4 bits are for input; upper 4 bits are for output. (8 pins) i/o / output i/o / input i/o standby release input function can be specified in 1-bit units. (8 pins) serial (asynchronous communication) during flash on-board write. analog input for a/d converter. (12 pins) serial data (ch3) input. serial data (ch3) output. serial clock (ch3) i/o. remote control receive circuit input. data i/o of i 2 c bus interface (ch0). clock i/o of i 2 c bus interface (ch0). data i/o of i 2 c bus interface (ch1). clock i/o of i 2 c bus interface (ch1). external event input for 8-bit timer/counter. serial chip select (ch0) input. serial data (ch0) input. serial data (ch0) output. serial clock (ch0) i/o. 8-bit timer/counter output. 16-bit timer (ch0) output. flash mode setting pins
7 CXP921F064A symbol i/o functions (port g) 8-bit i/o port. i/o can be specified in 1-bit units. (8 pins) (port j) 8-bit i/o port. i/o can be specified in 1-bit units. (8 pins) standby release input function can be specified in 1-bit units. (8 pins) i/o / input i/o / input i/o / output i/o / i/o i/o / input i/o / input i/o / output i/o / output output / output output / output input / input input / input / input input / input input / input input / input input i/o / input / input pg0/cs1 pg1/si1 pg2/so1 pg3/sck1 pg4/cs2 pg5/si2 pg6/so2 pg7/sck2 ph0/rto0 to ph4/rto4 ph5/xout ph6/int0 ph7/int1/ tetc pi0/int2 to pi5/int7 pi6/nmi pi7/an0 an1 to an3 pj0/an4/ ks8 to pj7/an11/ ks15 rst av dd av ref0 av ref1 av ss v dd v ss pwe input input input input (port h) 8-bit port. lower 6 bits are for output; upper 2 bits are for input. (8 pins) (port i) 8-bit input port. (8 pins) serial chip select (ch1) input. serial data (ch1) input. serial data (ch1) output. serial clock (ch1) i/o. serial chip select (ch2) input. serial data (ch2) input. serial data (ch2) output. serial clock (ch2) output. real-time pulse generator output. (5 pins) clock output for clock prescaler buzzer. external interrupt input. (8 pins) non-maskable external interrupt input. analog input for a/d converter. (12 pins) connects a crystal for main clock oscillation. (when the clock is supplied externally, input it to extal and input an opposite phase clock to xtal.) connects a crystal for sub clock oscillation. (when the clock is supplied externally, input it to tex and input an opposite phase clock to tx.) system reset. active at "l" level. positive power supply for a/d converter. reference voltage input for a/d converter (ch0). reference voltage input for a/d converter (ch1). gnd for a/d converter. positive power supply. (connect all three v dd pins to positive power supply.) gnd (connect all four vss pins to gnd.) permits erasure and write of incorporated flash eeprom. extal xtal tex tx input input flash mode setting pins
8 CXP921F064A i/o circuit format for pins pin circuit format after a reset pa0/an12 to pa7/an19 hi-z internal data bus input protection circuit ip rd pa register "0" after a reset pasl register "0" after a reset a/d converter input multiplexer pb0/an20 to pb3/an23 hi-z internal data bus ip rd pb register "0" after a reset pbsl register "0" after a reset a/d converter input multiplexer pb4/si3 pb7/rmc hi-z internal data bus ip rd pb register "0" after a reset pbsl register "0" after a reset si3, rmc cmos schmitt input
9 CXP921F064A pb5/so3 hi-z pb register "0" after a reset so3 mpx pbsl register "0" after a reset so3 output enable internal data bus rd 0 1 pc0/sda0 pc1/scl0 pc2/sda1 pc3/scl1 hi-z pc register undefined after a reset pulc register "0" after a reset sda0, scl0, sda1, scl1 pcsl register "0" after a reset pcd register "0" after a reset sda0, scl0 sda1, scl1 cmos schmitt input ? pull-up transistor approximately 15k ? (v dd = 2.7 to 3.3v) ip mpx internal data bus rd ? 1 0 pb6/sck3 hi-z pb register "0" after a reset sck3 mpx pbsl register "0" after a reset sck3 output enable sck3 internal data bus rd cmos schmitt input ip 0 1 pin circuit format after a reset
10 CXP921F064A pd0/ks0 to pd7/ks7 hi-z pe0/txd hi-z ip pd register undefined after a reset pdd register "0" after a reset ? large current drive 5ma (v dd = 2.7 to 3.3v) internal data bus standby release rd ? ip pe register undefined after a reset ped register "0" after a reset internal data bus txd output enable rd txd mpx 1 0 pin circuit format after a reset pc4 to pc7 hi-z pc register undefined after a reset pulc register "0" after a reset pcd register "0" after a reset ? pull-up transistor approximately 15k ? (v dd = 2.7 to 3.3v) ip internal data bus rd ?
11 CXP921F064A hi-z pf0 internal data bus rd ip hi-z pf1/ec internal data bus ec cmos schmitt input rd ip hi-z pf2/cs0 pf3/si0 internal data bus cs0, si0 cmos schmitt input rd ip pfsl register "0" after a reset pe1/rxd hi-z ip pe register undefined after a reset ped register "0" after a reset rxd internal data bus rd pe2 to pe7 hi-z ip pe register undefined after a reset ped register "0" after a reset internal data bus rd pin circuit format after a reset
pf6/to/ tetb pf7/tmo/ teta "h" level ("h" level at on resistance of pull-up transistor during a reset.) pf register "0" after a reset to, tmo mpx pfsl register "0" after a reset pf register write reset internal data bus rd q s r 1 0 ? pull-up transistor approximately 150k ? (v dd = 2.7 to 3.3v) ? teta, tetb 12 CXP921F064A pf4/so0 hi-z pf register "0" after a reset so0 mpx pfsl register "0" after a reset so0 output enable pf register write reset internal data bus rd q s r 1 0 pf5/sck0 hi-z pf register "0" after a reset sck0 mpx pfsl register "0" after a reset sck0 output enable pf register write reset sck0 internal data bus rd cmos schmitt input ip q s r 1 0 pin circuit format after a reset
13 CXP921F064A pg2/so1 pg3/sck1 pg6/so2 pg7/sck2 hi-z pg register undefined after a reset pgsl register "0" after a reset mpx pgd register "0" after a reset sck1 internal data bus rd so1, sck1 so2, sck2 output enable so1, sck1 so2, sck2 cmos schmitt input (pg3 only) ip 1 0 pg0/cs1 pg1/si1 pg4/cs2 pg5/si2 hi-z ip pg register undefined after a reset pgd register "0" after a reset pgsl register "0" after a reset internal data bus cs1, si1 cs2, si2 rd cmos schmitt input pin circuit format after a reset ph0/rto0 to ph4/rto4 hi-z ph register undefined after a reset rto0 to rto4 ph register write reset q s r internal data bus rd
14 CXP921F064A ph5/xout hi-z ph register write reset q s r internal data bus rd mpx xout 1 0 ph register undefined after a reset phsl register "0" after a reset ph6/int0 to ph7/int1/ tetc hi-z internal data bus interrupt circuit cmos schmitt input rd tetc ip pi0/int2 to pi5/int7 hi-z internal data bus interrupt circuit cmos schmitt input rd ip pin circuit format after a reset pi6/nmi hi-z internal data bus interrupt circuit (nmi) cmos schmitt input rd ip pisl register "0" after a reset pi7/an0 hi-z internal data bus a/d converter rd ip pisl register "0" after a reset input multiplexer an1 to an3 hi-z ip a/d converter input multiplexer
15 CXP921F064A pj0/an4/ ks8 to pj7/an11/ ks15 hi-z ip pj register undefined after a reset pjd register "0" after a reset pjsl register "0" after a reset internal data bus standby release a/d converter rd input multiplexer pin circuit format after a reset extal xtal oscillation diagram shows circuit configuration during oscillation. feedback resistor is removed during stop mode, and xtal is driven at "h" level. extal xtal oscillation stop control ip timing generator tex tx oscillation oscillation stop control timing generator, clock prescaler tx is driven at hi-z during stop mode. tex tx ip ip
16 CXP921F064A "l" level (during a reset) rst ip cmos schmitt input ? pull-up transistor approximately 30k ? (v dd = 2.7 to 3.3v) ? mask option op internal reset circuit pin circuit format after a reset hi-z pwe ip flash eeprom circuit ? input protection only to negative voltage ?
17 CXP921F064A absolute maximum ratings item supply voltage input voltage output voltage high level output current high level total output current low level output current low level total output current operating temperature storage temperature allowable power dissipation v dd av dd av ref av ss v in v out i oh i oh i ol i olc i ol topr tstg p d 0.3 to +4.6 av ss to +4.6 ? 1 av ss to +4.6 ? 1 0.3 to +0.3 0.3 to +4.6 ? 2 0.3 to +4.6 ? 2 5 50 15 20 130 20 to +75 ? 4 55 to +150 600 380 500 v v v v v v ma ma ma ma ma c c mw mw mw output (value per pin) total for all output pins all pins excluding large current output pins (value per pin) large current output pins ? 3 (value per pin) total for all output pins qfp-100p-l01 lqfp-100p-l01 lflga-104p-02 symbol rating unit remarks ? 1 av dd and av ref must be the same voltage with v dd . ? 2 v in and v out must not exceed v dd + 0.3v. ? 3 the large current drive transistor is n-ch transistor of pd. ? 4 operating temperature range during write/erasure of flash memory is ta = 0 to 50 c. note) usage exceeding absolute maximum ratings may permanently impair the lsi. normal operation should be conducted under the recommended operating conditions. exceeding these conditions may adversely affect the reliability of the lsi. (v ss = 0v reference)
18 CXP921F064A item supply voltage v dd av dd av ref v ih v ihs v ihex v il v ils v ilex topr high level input voltage low level input voltage symbol min. 2.7 2.2 2.2 2.0 2.7 2.7 0.7v dd 0.8v dd 0.7v dd 0 0 0.3 20 3.3 3.3 3.3 3.3 3.3 3.3 v dd v dd v dd + 0.3 0.2v dd 0.2v dd 0.3v dd +75 v v v v v v v v v v v v c guaranteed operation range with tex clock guaranteed operation range for clock mode guaranteed data hold range during stop mode ? 1 ? 1 ? 2 cmos schmitt input ? 3 extal, tex ? 2 cmos schmitt input ? 3 extal, tex max. unit remarks ? 1 av dd and av ref must be the same voltage with v dd . ? 2 pc4 to pc7, pd, pe, pf0, pg2, pg6, pi7, pj for normal input port. ? 3 pb4, pb6, pb7, pc0 to pc3, pf1 to pf3, pf5, pg0, pg1, pg3 to pg5, ph6, ph7, pi0 to pi6, rst. (vss = 0v reference) recommended operating conditions operating temperature
19 CXP921F064A electrical characteristics dc characteristics (topr = 20 to +75 c, vss = 0v reference) high level output voltage v oh v ol i ihe i ile i ilr i il low level output voltage pa, pb, pd, pe, pf4 to pf7, pg, ph0 to ph5, pj pc rst ? 1 pc ? 2 pa, pb , pd to pg , ph6, ph7 , pi, pj , an1 to an3 , tex item symbol pins conditions min. supply current ? 3 i dd1 ? 4 i iz input current typ. max. unit v dd = 3.0 0.3v, 20mhz crystal oscillation, a/d off state (c 1 = c 2 = 10pf) i dd2 v dd = 3.0 0.3v, 32khz crystal oscillation, 20mhz oscillation stop, a/d off state (c 1 = c 2 = 47pf) i dds1 v dd = 3.0 0.3v, 20mhz crystal oscillation, a/d off state (c 1 = c 2 = 10pf), sleep mode v dd , v ss v dd = 3.3v, v il = 0.3v v dd = 2.7v, v ih = 2.4v v dd = 3.3v, v i = 0, 3.3v i/o leakage current pc ? 2 i loh v dd = 3.3v, v ih = 3.3v open drain output leakage current (n-ch tr. off state) 0.3 0.3 0.9 1.0 20 70 7 12 7 1.0 20 20 250 250 10 10 26 150 12 70 50 40 v a a a a a a a ma a ma a a a v dd = 2.7v, i oh = 0.15ma v dd = 2.7v, i oh = 0.5ma v dd = 2.7v, i oh = 0.05ma 2.4 2.0 1.3 v v v v dd = 2.7v, i ol = 1.2ma v dd = 2.7v, i ol = 1.6ma v dd = 2.7v, i ol = 2.0ma v dd = 2.7v, i ol = 3.0ma v dd = 2.7v, i ol = 5.0ma v dd = 3.3v, v ih = 3.3v v dd = 3.3v, v il = 0.3v 0.3 0.5 0.3 0.5 v v v v pa, pb , pc4 to pc7, pe , pf4 to pf7, pg, ph0 to ph5, pj pc0 to pc3 (scl0, scl1 , sda0, sda1) pd extal i dds2 v dd = 3.0 0.3v, 32khz crystal oscillation, 20mhz oscillation stop, a/d off state (c 1 = c 2 = 47pf), sleep mode i dds3 v dd = 3.0v, 32khz crystal oscillation, 20mhz oscillation stop (c 1 = c 2 = 47pf), clock mode i dds4 v dd = 3.0v, stop mode
20 CXP921F064A item symbol pins conditions min. typ. max. unit clock 1mhz 0v for all pins excluding measured pins c in input capacitance pa, pb0 to pb4 , pb6, pb7 , pc to pe , pf0 to pf3 , pf5, pg, ph6 , ph7, pi, pj , an1 to an3 , extal, tex , rst 10 20 pf ? 1 rst specifies the input current when pull-up resistor has been selected; the leakage current when no resistor has been selected. ? 2 pc specifies the input current when pull-up resistor has been selected; the leakage current when no resistor has been selected. ? 3 when all output pins are open. ? 4 when the upper two bits (pck1, pck0) of the clock control register (clc: 0002feh) are set to "00" and the lsi is operated in high-speed mode (2 frequency dividing clock).
21 CXP921F064A ac characteristics (1) clock timing (topr = 20 to +75 c, v dd = 2.7 to 3.3v, vss = 0v reference) item main clock base oscillation frequency main clock base oscillation input pulse width main clock base oscillation input rise time, fall time sub clock base oscillation frequency sub clock base oscillation input pulse width sub clock base oscillation input rise time, fall time f ex t xh t xl t xr t xf f tex t th t tl t tr t tf extal , xtal extal extal tex , tx tex tex fig.1 fig.1, fig.2 external clock drive fig.1, fig.2 external clock drive fig.1 fig.1, fig.2 external clock drive fig.1, fig.2 external clock drive v dd = 3.0 0.3v v dd = 3.0 0.3v v dd = 3.0 0.3v v dd = 2.2 to 3.3v v dd = 3.3v v dd = 2.2v v dd = 3.3v v dd = 2.2v 15 20 32.735 15.3 15.3 20.5 14 33.096 200 200 mhz ns ns khz s s ns ns symbol pins conditions min. max. 20 32.768 typ. unit note) t sys indicates the four values below according to the upper two bits (pck1, pck0) of the clock control register (clc: 0002feh) during main mode and t sys = 2/f tex = 61.04s during sub mode. t sys [ns] = 2/f ex (pck1, pck0 = 00), 4/f ex (pck1, pck0 = 01), 8/f ex (pck1, pck0 = 10), 16/f ex (pck1, pck0 = 11) extal 1/f ex t xh t xf t xl t xr 0.7v dd 0.3v dd tex 1/f tex t th t tf t tl t tr 0.7v dd 0.3v dd fig.2. oscillator connection and clock applied conditions oscillator connection example of sub oscillation circuit connection example of external clock tex tx (tex) extal (tx) xtal 74hc04 oscillator connection example of main oscillation circuit extal xtal fig.1. clock timing
22 CXP921F064A fig.3. event count input timing ec t eh t el 0.8v dd 0.2v dd (2) event count input (topr = 20 to +75 c, v dd = 2.7 to 3.3v, vss = 0v reference) item event count input clock pulse width t eh , t el ec fig.3 t sys + 100 ns symbol pins conditions min. max. unit fig.4. interruption input timing 0.2v dd t ih t il 0.8v dd nmi int0 to int7 ks0 to ks15 0.2v dd rst t rst fig.5. reset input timing (3) interruption and reset input (topr = 20 to +75 c, v dd = 2.7 to 3.3v, vss = 0v reference) item external interruption high, low level width t ih , t il t rst nmi int0 to int7 ks0 to ks15 int4 to int7 rst main mode sub mode sleep mode clock mode stop mode noise filter selected fig.5 ps4 ps6 ns s ns ns t sys + 100 1 2 t sys + 100 32/f ex + 100 128/f ex + 100 50/f ex reset input low level width symbol pins conditions min. max. unit
23 CXP921F064A conversion time sampling time reference input voltage analog input voltage av ref current t conv t samp v ref v ian i ref i refs av ref0 av ref1 v dd = av dd = av ref = 3.0v v dd = av dd = av ref linearity error absolute error resolution 3.3 av ref 1.5 10 34 t sys 9 t sys 2.7 0 main mode sub mode clock mode stop mode during adc off state ? item symbol pins conditions min. typ. max. unit bits (4) a/d converter characteristics (topr = 20 to +75 c, v dd = av dd = av ref = 2.7 to 3.3v, vss = avss = 0v reference) 8 1 lsb lsb s s v v ma a 3 1.1 av ref an0 to an23 fig.6. definition of a/d converter terms ffh feh 01h 00h analog input linearity error digital conversion value ffh (100h) feh 01h 00h analog input digital conversion value absolute error av ref absolute error v zt ? 1 v ft ? 2 ? 1 v zt : value at which the digital conversion value changes from 00h to 01h and vice versa. ? 2 v ft : value at which the digital conversion value changes from feh to ffh and vice versa ? when bit 14 (adoff) of a/d control status register (adcs0: 00013ch, adcs1: 00014ch) is specified to "1". note) av dd and av ref must be the same voltage with v dd .
24 CXP921F064A external start transfer mode (sck = output mode) external start transfer mode (sck = output mode) external start transfer mode external start transfer mode external start transfer mode input mode output mode input mode output mode sck input mode sck output mode sck input mode sck output mode sck input mode sck output mode sck input mode sck output mode note) the load condition for the sck output mode and so output delay time is 100pf. (5) serial transfer (ch0, ch1, ch2) (topr = 20 to +75 c, v dd = 2.7 to 3.3v, vss = 0v reference) item cs sck delay time cs sck float delay time cs so delay time cs so float delay time cs high level width sck cycle time sck high, low pulse width si input data setup time (for sck ) si input data hold time (for sck ) sck so delay time minimum interval time t dcsk t dcskf t dcso t dcsof t whcs t kcy t kh t kl t sik t ksi t kso t int symbol pins min. 1.5 t sys + 200 1.5 t sys + 200 1.5 t sys + 200 1.5 t sys + 200 t sys + 150 100 t sys + 100 2 t sys + 200 16/f ex t sys + 100 8/f ex 100 100 200 t sys t sys + 100 t sys + 100 3 t sys + 100 8/f ex 100 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns max. unit conditions sck0 sck1 sck2 sck0 sck1 sck2 so0 so1 so2 cs0 cs1 cs2 cs0 cs1 cs2 sck0 sck1 sck2 sck0 sck1 sck2 si0 si1 si2 si0 si1 si2 so0 so1 so2 sck0 sck1 sck2
25 CXP921F064A fig.7. serial transfer ch0, ch1, ch2 timing cs0 cs1 cs2 sck0 sck1 sck2 si0 si1 si2 so0 so1 so2 sck0 sck1 sck2 t int 0.8v dd 0.2v dd 0.8v dd t dcsof 0.2v dd 0.8v dd t sik t ksi 0.2v dd 0.8v dd 0.2v dd 0.8v dd t kh t dcskf t whcs t kl t dcsk t kcy t kso output data input data t dcso
26 CXP921F064A input mode output mode input mode output mode sck input mode sck output mode sck input mode sck output mode sck input mode sck output mode note) the load condition for the sck output mode and so output delay time is 100pf. (6) serial transfer (ch3) [sio mode] (topr = 20 to +75 c, v dd = 2.7 to 3.3v, vss = 0v reference) item sck cycle time sck high, low pulse width si input data setup time (for sck ) si input data hold time (for sck ) sck so delay time t kcy t kh t kl t sik t ksi t kso symbol pins min. t sys + 150 100 2 t sys + 200 16/f ex t sys + 100 8/f ex 100 100 200 t sys + 100 200 ns ns ns ns ns ns ns ns ns ns max. unit conditions sck3 si3 so3 t kcy 0.8v dd 0.8v dd 0.2v dd 0.2v dd 0.8v dd 0.2v dd t kl t sik t kso t ksi t kh sck3 si3 so3 input data output data fig.8. serial transfer ch3 timing (sio mode)
27 CXP921F064A ? when lower 2 bits (sck1, sck0) of serial mode register (siom3: 0001a4h) is specified to "00". note) the load condition for the so output delay time is 100pf. (7) serial transfer (ch3) [special mode] (topr = 20 to +75 c, v dd = 2.7 to 3.3v, vss = 0v reference) item so cycle time ? si input setup time si input hold time input start bit high level width si so delay time t lcy t lsu t lhd t lsbh t lio symbol pins min. 1 2 2 1 typ. 104 s max. unit conditions so3 si3 si3 si3 si3 so3 start bit output data bit input data bit so3 t lcy t lcy 0.5v dd 0.2v dd si3 t lsu t lcy /2 t lhd 0.8v dd fig.9. serial transfer ch3 timing (special mode) input data bit output data bit si3 t lsbh 0.2v dd 0.8v dd 0.5v dd so3 t lcy /2 t lsu t lhd t lsu t lhd t lcy t lio t lcy t lcy fig.10. serial transfer ch3 timing (special mode) f ex = 20mh z communication slave mode
28 CXP921F064A ? due to the total capacitance of the bus. (8) i 2 c bus (ch0, ch1) (topr = 20 to +75 c, v dd = 2.7 to 3.3v, vss = 0v reference) item sck clock frequency bus free time between stop and start conditions hold time under (resend) start condition hold time in scl clock low state hold time in scl clock high state setup time under (resend) start condition data hold time data setup time scl, sda signal output rise time scl, sda signal output fall time setup time under stop condition scl0 scl1 sda0 sda1 sda0, sda1 scl0, scl1 scl0 scl1 scl0 scl1 sda0, sda1 scl0, scl1 sda0, sda1 scl0, scl1 sda0, sda1 scl0, scl1 sda0, sda1 scl0, scl1 sda0, sda1 scl0, scl1 sda0, sda1 scl0, scl1 t scl t buf t hd;sta t low t high t su;sta t hd;dat t su;dat t rd t rc t fd t fc t su;sto symbol pins min. standard mode high-speed mode 400 0.9 300 300 0 1.3 0.6 1.3 0.6 0.6 0 100 20 + ? 20 + ? 0.6 khz s s s s s s ns ns ns s max. min. 100 1000 300 0 4.7 4.0 4.7 4.0 4.7 0 250 4.0 max. unit sda0 sda1 scl0 scl1 t buf t su;dat t hd;sta t scl t fd t rd t rc t fc t low t hd;sta t hd;dat t high t su;sta t su;sto fig.11. i 2 c bus timing
29 CXP921F064A (9) remote control reception (topr = 20 to +75 c, v dd = 2.7 to 3.3v, vss = 0v reference) item remote control receive high, low level width t rmc rmc main mode sub mode ps5 selected ps7 selected ps9 selected 32k selected ns 128/f ex + 100 512/f ex + 100 2048/f ex + 100 4/f tex + 100 8/f tex + 100 symbol pins conditions min. max. unit 0.8v dd rmc 0.2v dd t rmc t rmc fig.12. remote control signal input timing
30 CXP921F064A extal xtal c 1 c 2 rd tex tx c 1 c 2 rd extal (i) main oscillation circuit (ii) main oscillation circuit (iii) sub oscillation circuit xtal c 1 c 2 rd rf fig.13. recommended oscillation circuit appendix manufacturer murata mfg co., ltd. river eletec co., ltd. kinseki ltd. hc-49/u03 hc-49/u-s tdk corporation model csa12.0mtz csa16.00mxz040 csa20.00mxz040 cst12.0mtw ? cst16.00mxw0c3 ? ccr12.0msc5 ? ccr16.0msc6 ? ccr20.0msc6 ? 12.0 16.0 20.00 12.0 16.0 12.00 12.0 16.0 20.0 12.0 16.0 20.0 30 15 10 30 15 10 12 12 12 20 (20%) 10 (20%) 10 (20%) 30 15 10 30 15 10 12 12 12 20 (20%) 10 (20%) 10 (20%) 0 0 0 0 0 220 1.0k 470 390 f ex (mhz) c 1 (pf) c 2 (pf) rd ( ? ) circuit example remarks (i) (ii) (i) (ii) 150k rf = 10m ? cl = 12.5pf item content reset pin pull-up resistor non-existent existent mask option table ? indicates types with on-chip grounding capacitor (c 1 , c 2 ). ccr ??? : surface mounted type ceramic oscillator. cl : load capacitor (i) 0 cl = 12pf vtc-200 sp-t seiko instruments inc. 20 18 (iii) 32.768kh z cl = 10pf
31 CXP921F064A notes on using the pf7 pin the pf7 pin of the flash eeprom incorporated version provides a flash mode setting function. note the following points when using this pin. 1. although the pf7 pin output is made at high level during a reset, the pin is driven at a relatively high impedance of about 150k ? . note that v oh does not fall below 0.7v dd due to partial pressure with the load impedance of the external circuit. 2. when the software reset function is used, the pf7 pin may not rise enough during a reset. switching the pf7 pin to high output or connecting pull-up resistor is recommended before software reset is executed. be sure to set the pf7 pin to 0.7v dd or more during this interval. rst pf7 flash mode normal operation description of flash memory performance item operational mode programming method erase method data hold performance off-board parallel, on-board serial page units (512-bit units) all erase 10 years ? 1 item write time ? 2 erase time program/erase count min. typ. 8 max. 12 50 100 unit ms/512 bits ms count ? 1 when data is used and stored under recommended operating conditions. (ta = 0 to +50 c, v dd = 2.7 to 3.3v, v ss = 0v reference) ? 2 when write clock f fck = 10mhz is used in off-board parallel mode. fig.14. status of the pf7 pin during a reset
32 CXP921F064A on-board write by performing steps 1) through 3) below on the user's hardware, the microcontroller can be reset/started and the flash eeprom overwritten, 1) fix the mode control pin using external hardware pf7/teta pin fix to l level pf6/tetb pin fix to h level or leave open ph7/tetc pin fix to h level pwe pin fix to h level 2) connect the microcontroller and sfp-2 using the specified connection method. 3) overwrite the flash eeprom from the sfp-2. v in 5 rxd 2 txd v dd txd gnd 1, 6 v ss v pp 7 rxd 3 res res 4 (not used) on only while flash eeprom overwrite reset circuit CXP921F064A txd/pe0 v dd teta tetb tetc rst v ss pwe rxd/pe1 sfp-2 asynchronous communications connector (async: pin 7) user hardware sfp-2 fig.15. example of connection between the sfp-2 and user hardware 1. the pwe pin provides a function for writing/erasing the flash eeprom. fix this pin to h level to overwrite or erase the flash eeprom. fix this pin to l level to forcibly prohibit overwriting. 2. since an amp-ct receptal 173977-7 is used as the connector for the flash programmer (sfp-2), an amp- ct connector 175489-7 is recommended for the user hardware. ? the sfp-2 is manufactured and sold by mitec systems, inc.
33 CXP921F064A off-board write the sfp-2 is used to write data. the setting is as follows. device type rom area spc970flsh#0 adapter start : fc0000 end : ffffff for details on how to write data using the sfp-2, refer to the sfp-2 user's manual.
34 CXP921F064A characteristics curve 20 18 16 14 i dd supply current [ma] 12 10 8 6 2 2.1 2.4 2.7 v dd supply voltage [v] i dd vs. v dd (f ex = 20mhz, topr = 25 c, typical) 3.3 3 3.6 3.9 4 20 18 16 14 12 i dd supply current [ma] 10 8 6 4 2 2.1 2.4 2.7 3 v dd supply voltage [v] i dd vs. v dd (f ex = 20mhz, topr = 25 c, typical) 3.3 3.6 3.9 0 30 25 i dd supply current [ a] 20 15 10 5 0 2.1 2.4 2.7 v dd supply voltage [v] i dd vs. v dd (f tex = 32khz, topr = 25 c, typical) 3.3 3 3.6 3.9 20 18 16 14 12 i dd supply current [ma] 10 8 6 4 2 0510 f ex system clock [mhz] i dd vs. f ex (v dd = 3v, topr = 25 c, typical) 15 20 25 0 20 18 16 14 12 i dd supply current [ma] 10 8 6 4 2 510 f ex system clock [mhz] i dd vs. f ex (v dd = 3v, topr = 25 c, typical) 15 20 25 0 0 2 frequency dividing mode 4 frequency dividing mode 8 frequency dividing mode 16 frequency dividing mode 32khz mode (instruction execution) 32khz sleep mode 32khz clock mode sleep mode (2 frequency division) sleep mode (4 frequency division) sleep mode (8 frequency division) sleep mode (16 frequency division) 2 frequency dividing mode 4 frequency dividing mode 8 frequency dividing mode 16 frequency dividing mode sleep mode (2 frequency division) sleep mode (4 frequency division) sleep mode (8 frequency division) sleep mode (16 frequency division)
35 CXP921F064A package outline unit: mm sony code eiaj code jedec code package material lead treatment lead material package mass epoxy resin solder plating 42/copper alloy package structure 23.9 0.4 qfp-100p-l01 100pin qfp (plastic) 20.0 0.1 + 0.4 0.15 0.05 + 0.1 15.8 0.4 17.9 0.4 14.0 0.1 + 0.4 2.75 0.15 + 0.35 a 0.65 m 0.13 qfp100-p-1420 1.7g 1 100 81 80 51 50 31 30 0.3 0.1 + 0.15 detail a 0 to 10 0.8 0.2 (16.3) 0.15 0.1 0.05 + 0.2
36 CXP921F064A package outline unit: mm 100pin lqfp (plastic) 25 26 51 50 75 76 1 100 sony code eiaj code jedec code package material lead treatment lead material package mass epoxy resin solder plating 42 / copper alloy package structure detail a lqfp-100p-l01 p-lqfp100-14x14-0.5 16.0 0.2 14.0 0.1 0.5 b (0.22) a 1.5 ?0.1 + 0.2 0.5 0.2 (15.0) 0? to 10? 0.1 0.1 0.5 0.2 0.1 note: dimension " ? " does not include mold protrusion. 0.7g 0.13 m b = 0.18 ?0.03 ( 0.18 ) (0.127) + 0.08 0.127 ?0.02 + 0.05 detail b ? b 100pin lqfp (plastic) 25 26 51 50 75 76 1 100 sony code eiaj code jedec code package material lead treatment lead material package mass epoxy resin solder plating 42 / copper alloy package structure detail a lqfp-100p-l01 p-lqfp100-14x14-0.5 16.0 0.2 14.0 0.1 0.5 b (0.22) a 1.5 0.1 + 0.2 0.5 0.2 (15.0) 0 ? to 10 ? 0.1 0.1 0.5 0.2 0.1 note: dimension " ? " does not include mold protrusion. 0.7g 0.13 m b = 0.18 0.03 ( 0.18 ) (0.127) + 0.08 0.127 0.02 + 0.05 detail b ? b lead specifications item lead material alloy 42 lead treatment sn-bi 2.5% lead treatment thickness 5-18 m spec.
37 CXP921F064A package outline unit: mm sony code eiaj code jedec code package mass package structure lflga-104p-02 organic substrate 0.4g package material terminal treatment terminal material gold plating nickel plating 104pin lflga lflga104-p-1212 detail x 1.4max s s 0.20 s 0.10 0.01 x pin 1 index 12.0 0.15 a s 12.0 0.15 b s 0.20 x4 1 2 3456 78 910111213 103 0.40 0.05 0.08 m sab a b 0.8 a b c d e f g h j k l m n 1.2 0.8 1.2 0.4 0.4 1.6 1.6 sony corporation

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